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1 datasheet dual, high speed mosfet driver isl55110, isl55111 the isl55110 and isl55111 ar e dual high speed mosfet drivers intended for applications requiring accurate pulse generation and buffering. ta rget applications include ultrasound, ccd imagin g, piezoelectric distance sensing and clock generation circuits. with a wide output voltage rang e and low on-resistance, these devices can drive a variety of resistive and capacitive loads with fast rise and fall times, allowing high-speed operation with low skew, as required in large ccd array imaging applications. the isl55110, isl55111 are co mpatible with 3.3v and 5v logic families and incorporate tightly controlled input thresholds to minimize the effect of input rise time on output pulse width. the isl55110 has a pair of in-phase drivers while the isl55111 has two drivers operating in anti-phase. isl55110 and isl55111 have a power-down mode for low power consumption during equi pment standby times, making it ideal for portable products. the isl55110 and isl55111 are available in 16 ld exposed pad qfn packaging and 8 ld tssop. both devices are specified for operation over the full -40c to +85c temperature range. features ? 5v to 12v pulse amplitude ? high current drive 3.5a ? 6ns minimum pulse width ? 1.5ns rise and fall times, 100pf load ?low skew ? 3.3v and 5v logic compatible ? in-phase (isl55110) and anti-phase outputs (isl55111) ? small qfn and tssop packaging ?low quiescent current ? pb-free (rohs compliant) applications ? ultrasound mosfet driver ? ccd array horizontal driver ? clock driver circuits related literature ? an1283 , ?isl55110_11eval1z, isl55110_11eval2z evaluation board user's manual? isl55110 and isl55111 dual driver vh oa ob in-a o o o o o in-b o o gnd o pd o vdd o enable -qfn* *enable available in qfn package only **isl55111 in-b is inverting ** figure 1. functional block diagram caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2006-2008, 2011-2015. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. january 29, 2015 fn6228.8
isl55110, isl55111 2 fn6228.8 january 29, 2015 submit document feedback pin configurations isl55110 (16 ld qfn) top view isl55111 (16 ld qfn) top view isl55110 (8 ld tssop) top view isl55111 (8 ld tssop) top view 16 15 14 13 ob gnd vh oa 1 2 3 4 12 11 10 9 vdd enable pd in-b 5678 in-a nc nc nc nc nc nc nc ep 16 15 14 13 ob gnd vh oa 1 2 3 4 12 11 10 9 vdd enable pd in-b 5678 in-a nc nc nc nc nc nc nc ep 6 7 8 5 1 2 3 4 vdd pd in-b in-a ob vh oa gnd 6 7 8 5 1 2 3 4 vdd pd in-b in-a ob vh oa gnd pin descriptions 16 ld qfn 8 ld tssop pin function 11vddlogic power. 10 6 vh driver high rail supply. 11 7 gnd ground, return for both vh rail and vdd logic supply. this is also the potential of the qfn?s exposed pad (ep). 3 2 pd power-down. active logic high places part in power-down mode. 2-enable qfn packages only. when the enable pin is low, the device will operate normally (outputs controlled by the inputs). when the enable pin is tied high, the output will be tri-stated. in other words, it will act as if it is open or floating regardless of what is on the in-x pins. this provides high-speed enable control over the driver outputs. 5 4 in-a logic level input that drives oa to vh rail or ground. not inverted. 4 3 in-b, in-b logic level input that drives ob to vh rail or grou nd. not inverted on isl55110, inverted on isl55111. 95oadriver output related to in-a. 12 8 ob driver output related to in-b. 6, 7, 8, 13, 14, 15, 16 -ncno internal connection. ep - ep exposed thermal pad. conn ect to gnd and follow good thermal pad layout guidelines.
isl55110, isl55111 3 fn6228.8 january 29, 2015 submit document feedback ordering information part number ( notes 1 , 2 , 3 ) part marking temp. range (c) package (rohs compliant) pkg. dwg. # isl55110irz 55110irz -40 to +85 16 ld qfn l16.4x4a isl55110ivz 55110 ivz -40 to +85 8 ld tssop m8.173 isl55111irz 55111irz -40 to +85 16 ld qfn l16.4x4a isl55111ivz 55111 ivz -40 to +85 8 ld tssop m8.173 isl55110eval1z tssop evaluation board isl55110eval2z qfn evaluation board ISL55111EVAL1Z tssop evaluation board isl55111eval2z qfn evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged pr oducts employ special pb-free material sets , molding compounds/die attach materials and 100% matte tin plate plus anneal (e3 termination finish, which is rohs complian t and compatible with both snpb and pb-free soldering operation s). intersil pb-free products are msl classified at pb-free peak reflow temperatures th at meet or exceed the pb-free requirements of ipc/jedec j std -020. 3. for moisture sensitivity level (msl), please see device information page for isl55110 , isl55111 . for more information on msl please see techbrief tb363 .
isl55110, isl55111 4 fn6228.8 january 29, 2015 submit document feedback absolute maximum ratings (t a = +25 c) thermal information v h to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.0v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5v vin-a, vin-b, pd, enable . . . . . . . . . . . . . . . . (gnd - 0.5v) to (v dd + 0.5v) oa, ob . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (gnd - 0.5) to (vh + 0.5v) maximum peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300ma esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3kv recommended operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c drive supply voltage (v h ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v to 13.2v logic supply voltage (v dd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150c thermal resistance ? ja (c/w) ? jc (c/w) 16 ld (4x4) qfn package ( notes 5 , 6 ) . . . 45 3.0 8 ld tssop package ( notes 4 , 7 ) . . . . . . . 140 46 maximum junction temperature (plastic package) . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 6. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 7. for ? jc , the ?case temp? location is taken at the package top center. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a dc electrical specifications v h = +12v, v dd = 2.7v to 5.5v, t a = +25c, unless otherwise specified. parameter description test conditions min ( note 8 )typ max ( note 8 )units logic characteristics vix_lh logic input threshold - low-to-high l ih = 1a: vin-a, vin-b 1.32 1.42 1.52 v vix_hl logic input threshold - high-to-low l il = 1a: vin-a, vin-b 1.12 1.22 1.32 v vhys logic input hysteresis vin-a, vin-b 0.2 v vih logic input high threshold pd 2.0 vdd v vil logic input low threshold pd 0 0.8 v vih logic input high threshold enable - qfn only 2.0 vdd v vil logic input low threshold enable - qfn only 0 0.8 v iix_h input current logic high vin-a, vin-b = vdd 10 20 na iix_l input current logic low vin-a, vin-b = 0v 10 20 na ii_h input current logic high pd = vdd 10 20 na ii_l input current logic low pd = 0v 10 15 na ii_h input current logic high enable = vdd (qfn only) 12 a ii_l input current logic low enable = 0v (qfn only) -25 na driver characteristics r ds driver output resistance oa, ob 3 6 i dc driver output dc current (>2s) 100 ma i ac peak output current design intent; verified via simulation. 3.5 a voh to vol driver output swing range oa or ob = ?1?, voltage referenced to gnd 313.2v
isl55110, isl55111 5 fn6228.8 january 29, 2015 submit document feedback supply currents i dd logic supply quiescent current pd = low 4.0 6.0 ma i dd-pdn logic supply power-down current pd = high 12 a ih driver supply quiescent current pd = low, outputs unloaded 15 a ih_pdn driver supply power-down current pd = high 2.5 a dc electrical specifications v h = +12v, v dd = 2.7v to 5.5v, t a = +25c, unless otherwise specified. (continued) parameter description test conditions min ( note 8 )typ max ( note 8 )units ac electrical specifications v h = +12v, v dd = +3.6v, t a = +25c, unless otherwise specified. parameter description test conditions min ( note 8 )typ max ( note 8 )units switching characteristics t r driver rise time figure 2 , oa, ob: cl = 100pf/1k 10% to 90%, voh - vol = 12v 1.2 ns t f driver fall time figure 2 , oa, ob: cl = 100pf/1k 10% to 90%, voh - vol = 12v 1.4 ns t r driver rise time figure 2 , oa, ob: cl = 1nf 10% to 90%, voh - vol = 12v 6.2 ns t f driver fall time figure 2 , oa, ob: cl = 1nf 10% to 90%, voh - vol = 12v 6.9 ns tpdr input to output propagation delay figure 3 , load 100pf/1k 10.9 ns tpdf input to output propagation delay 10.7 ns tpdr input to output propagation delay figure 3 , load 330pf 12.8 ns tpdf input to output propagation delay 12.5 ns tpdr input to output propagation delay figure 3 , load 680pf 14.5 ns tpdf input to output propagation delay 14.1 ns tskewr channel-to-channel tpdr spread with same loads both channels figure 3 , all loads <0.5 ns tskewf channel-to-channel tpdf spread with same loads both channels figure 3 , all loads <0.5 ns fmax maximum operating frequency 70 mhz tmin minimum pulse width 6 ns pd en power-down to power-on time 650 ns pd dis power-on to power-down time 40 ns t en enable time; enable switched high to low. 40 ns t dis disable time; enable switched low to high. 40 ns note: 8. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
isl55110, isl55111 6 fn6228.8 january 29, 2015 submit document feedback isl55110 input input rise and fall times 2ns c l 4.7f 0.1f ? output vh = 12v 10% 10% 90% t f 90% t r ? 0.4v 12v input +3v 0v output in-x in figure 2. test circuit; output rise (t r )/fall (t f ) times isl55110 input input rise and fall times 2ns c l 4.7f 0.1f ? output vh = 12v 50% 50% 50% 50% tpdr tpdf ? 0.4v 12v input +3v 0v output oa and ob isl55110 in-x in output oa isl55111 50% 50% 12v 0v output ob isl55111 t skew r = |tpdr chn a - tpdr chn b| figure 3. test circuit; propagation (tpd) delay typical performance curves (see ? typical performance curves discussion ? on page 11 ) figure 4. driver r on vs v h voltage (sourcing current) figure 5. driver r on vs v h voltage (sinking current) 7.0 6.3 5.6 4.9 4.2 3.5 2.8 2.1 1.4 0.7 0.0 345678910111213 v h , drive rail (v) +85c -40c r on () v dd = 3.6v i out = -50ma +25c 7.0 6.3 5.6 4.9 4.2 3.5 2.8 2.1 1.4 0.7 0.0 345678910111213 v h , drive rail (v) r on () +85c -40c v dd = 3.6v i out = +50ma +25c
isl55110, isl55111 7 fn6228.8 january 29, 2015 submit document feedback figure 6. r on vs v dd voltage (sourcing current) figure 7. r on vs v dd voltage (sinking current) figure 8. quiescent i dd vs v dd figure 9. operating i dd vs v h at 50mhz (no load) figure 10. quiescent i h vs v h figure 11. operating i h vs v h at 50mhz (no load) typical performance curves (see ? typical performance curves discussion ? on page 11 ) (continued) 4.00 3.66 3.33 2.66 2.33 2.00 2.5 3.5 4.5 5.5 v dd (v) v h = 5v r on ( ? ) i out = -50ma v h = 12v 4.00 3.66 3.33 2.66 2.33 2.00 2.5 3.5 4.5 5.5 v dd (v) v h = 12v r on ( ? ) i out = +50ma v h = 5v 5.0 4.6 4.2 3.8 3.4 3.0 2.5 3.5 4.5 5.5 v dd (v) i dd (ma) v h = 5v to 12v 10 9 8 7 6 5 4 3 2 1 0 4812 i dd (ma) v dd = 3.6v v h , drive rail (v) 100 90 80 70 60 50 40 30 20 10 0 4812 v h , drive rail (v) i h (a) v dd = 3.6v 200 180 160 140 120 100 80 60 40 20 0 4812 v h , drive rail (v) i h (ma) v dd = 3.6v
isl55110, isl55111 8 fn6228.8 january 29, 2015 submit document feedback figure 12. i dd vs frequency (dual channel, no load) figure 13. ih vs frequency (dual channel, no load) figure 14. vih logic thresholds vs v dd figure 15. vil logic thresholds vs v dd figure 16. t r vs temperature figure 17. t f vs temperature typical performance curves (see ? typical performance curves discussion ? on page 11 ) (continued) 15.0 13.5 12.0 10.5 9.0 7.5 6.0 4.5 3.0 1.5 0 50 66 100 124 128 toggle frequency (mhz) i dd (ma) v h = 5.0v v dd = 3.6v 200 180 160 140 120 100 80 60 40 20 0 50 100 128 toggle frequency (mhz) 66 124 i h (ma) v h = 5.0v v dd = 3.6v 1.5 1.4 1.3 1.2 1.1 1.0 2.5 3.5 4.5 5.5 v dd (v) -40c +85c logic (v) 1.5 1.4 1.3 1.2 1.1 1.0 2.5 3.5 4.5 5.5 v dd (v) logic (v) -40c +85c 10 9 8 7 6 5 4 3 2 1 0 -40 -10 +20 +50 +85 package temperature (c) rise time (ns) 330pf 680pf v dd = 3.6v v h = 12.0v 10 9 8 7 6 5 4 3 2 1 0 -40 -10 +20 +50 +85 package temperature (c) fall time (ns) v dd = 3.6v v h = 12.0v 680pf 330pf
isl55110, isl55111 9 fn6228.8 january 29, 2015 submit document feedback figure 18. tpdr vs temperature f igure 19. tpdf vs temperature figure 20. t r vs v dd figure 21. t f vs v dd figure 22. t r vs v h figure 23. t f vs v h typical performance curves (see ? typical performance curves discussion ? on page 11 ) (continued) 20 18 16 14 12 10 8 6 4 2 0 -40 -10 +20 +50 +85 package temp (c) propagation delay (ns) 680pf 330pf v dd = 3.6v v h = 12.0v 20 18 16 14 12 10 8 6 4 2 0 -40 -10 +20 +50 +85 package temp (c) propagation delay (ns) 680pf 330pf v dd = 3.6v v h = 12.0v 10 9 8 7 6 5 4 3 2 1 0 2.5 3.5 5.5 v dd (v) rise time (ns) v h = 12.0v 4.5 100pf/1k 330pf 680pf 1000pf 10 9 8 7 6 5 4 3 2 1 0 2.5 3.5 5.5 v dd (v) fall time (ns) v h = 12.0v 4.5 1000pf 100pf/1k 680pf 330pf 12.0 10.8 9.6 8.4 7.2 6.0 4.8 3.6 2.4 1.2 0.0 36 12 v h (v) rise time (ns) v dd = 3.3v 9 680pf 330pf 100pf/1k 1000pf 36 12 v h (v) fall time (ns) v dd = 3.3v 9 10.8 9.6 8.4 7.2 6.0 4.8 3.6 2.4 1.2 0.0 12.0 680pf 330pf 100pf/1k 1000pf
isl55110, isl55111 10 fn6228.8 january 29, 2015 submit document feedback figure 24. tpdr vs v dd figure 25. tpdf vs v dd figure 26. tpdr vs v h figure 27. tpdf vs v h figure 28. tskewr vs temperature f igure 29. tskewf vs temperature typical performance curves (see ? typical performance curves discussion ? on page 11 ) (continued) 20 18 16 14 12 10 8 6 4 2 0 2.5 3.5 v dd (v) propagation delay (ns) v h = 12.0v 4.5 1000pf 5.5 100pf/1k 20 18 16 14 12 10 8 6 4 2 0 2.5 3.5 5.5 v dd (v) propagation delay (ns) v h = 12.0v 4.5 1000pf 100pf/1k 20 18 16 14 12 10 8 6 4 2 0 36 12 v h (v) propagation delay (ns) v dd = 3.3v 9 1000pf 100pf/1k 20 18 16 14 12 10 8 6 4 2 0 36 12 v h (v) propagation delay (ns) v dd = 3.3v 9 1000pf 100pf/1k 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -40 -10 +20 +50 +85 package temp (c) tskewr (ns) 330pf 680pf v dd = 3.6v v h = 12.0v 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -40 -10 +20 +50 +85 package temp (c) tskewf (ns) 330pf 680pf v dd = 3.6v v h = 12.0v
isl55110, isl55111 11 fn6228.8 january 29, 2015 submit document feedback typical performance curves discussion r on the r on source is tested by placing the device in constant drive high condition and connecting a -50ma constant current source to the driver output. the voltage drop is measured from v h to driver output for r on calculations. the r on sink is tested by placing the device in constant driver low condition and connecting a +50ma constant current source. the voltage drop from driv er out to ground is measured for r on calculations. dynamic tests all dynamic tests are conducted with isl55110 and isl55111 evaluation board(s) (isl55110_11eval2z). driver loads are soldered to the evaluation boar d. measurements are collected with p6245 active fet probes and tds5104 oscilloscope. pulse stimulus is provided by hp8131 pulse generator. the isl55110 and isl55111 evaluation boards provide test point fields for leadless connect ion to either an active fet probe or differential probe. ?tp - in_a/_b? test points are used for monitoring pulse input stimulus. ?tp - oa/ob? allows monitoring of driver output waveforms. c 6 and c 7 are the usual placement for driver loads. r 3 and r 4 are not populated and are provided for user-specified, more complex load characterization. pin skew pin skew measurements are based on the difference in propagation delay of the two channels. measurements are made on each channel from the 50% point on the stimulus point to the 50% point on the dr iver output. the difference in the propagation delay for ch annel a and channel b is considered to be skew. both rising propagation delay an d falling propagation delay are measured and report as tskewr and tskewf. 50mhz tests 50mhz tests reported as no load actually include evaluation board parasitics and a single tek 6545 fet probe. however, no driver load components are installed and c 6 through c 9 and r 3 through r 6 are not populated. figure 30. tskewr vs v dd figure 31. tskewf vs v dd figure 32. tskewr vs v h figure 33. tskewf vs v h typical performance curves (see ? typical performance curves discussion ? on page 11 ) (continued) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2.5 3.5 5.5 v dd (v) skew (ns) v h = 12.0v 4.5 330pf 680pf 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2.5 3.5 5.5 v dd (v) skew (ns) v h = 12.0v 4.5 680pf 330pf 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 36 12 v h (v) skew (ns) v dd = 3.3v 9 680pf 330pf 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 36 12 v h (v) skew (ns) v dd = 3.3v 9 330pf 680pf
isl55110, isl55111 12 fn6228.8 january 29, 2015 submit document feedback general the most dynamic measurements are presented in three ways: 1. over-temperature with a v dd of 3.6v and v h of 12v. 2. at ambient with v h set to 12v and v dd data points of 2.5v, 3.5v, 4.5v and 5.50v. 3. the ambient tests are repeated with v dd of 3.3v and v h data points of 3v, 6v, 9v and 12v. figure 34. isl55110_11eval2z (qfn) evaluation board
isl55110, isl55111 13 fn6228.8 january 29, 2015 submit document feedback detailed description the isl55110 and isl55111 are dual high-speed mosfet drivers intended for applications requiring accurate pulse generation and buffering. target applications include ultrasound, ccd imaging, automotive piezoe lectric distance sensing and clock generation circuits. with a wide output voltage rang e and low on-resistance, these devices can drive a variety of resi stive and capacitive loads with fast rise and fall times, allowing high-speed operation with low skew as required in large ccd array imaging applications. the isl55110 and isl55111 are co mpatible with 3.3v and 5v logic families and incorporate tightly controlled input thresholds to minimize the effect of input ri se time on output pulse width. the isl55110 has a pair of in-phase drivers while the isl55111 has two drivers operating in anti-phase. both channels of the device have independent inputs to allow external time phasing if required. in addition to driving power mosfets, the isl55110 and isl55111 are well suited for othe r applications such as bus, control signal and clock drivers for large memory arrays on microprocessor boards, where the load capacitance is large and low propagation delays are required. other potential applications include peripheral power driv ers and charge pump voltage inverters. input stage the input stage is a high impedance buffer with rise/fall hysteresis. this means that the inputs will be directly compatible with both ttl and lower voltage logic over the entire v dd range. the user should treat the inputs as high-speed pins and keep rise and fall times to <2ns. output stage the isl55110 and isl55111 outputs are high-power cmos drivers swinging between ground and v h . at v h = 12v, the output impedance of the inverter is typically 3.0 . the high peak current capability of the isl55110 and isl55111 enables it to drive a 330pf load to 12v with a rise time of <3.0ns over the full temperature range. the output swing of the isl55110 and isl55111 comes within <30mv of the v h and ground rails. application notes although the isl55110 and isl55111 are simply dual level shifting drivers, there are several areas to which careful attention must be paid. grounding since the input and the high current output current paths both include the ground pin, it is very important to minimize any common impedance in the ground return. since the isl55111 has one inverting input, any common impedance will generate negative feedback and may degrade the delay times and rise and fall times. use a ground plane if possible or use separate ground returns for the input and ou tput circuits. to minimize any common inductance in the ground return, separate the input and output circuit ground returns as close to the isl55110 and isl55111 as possible. bypassing the rapid charging and discharging of the load capacitance requires very high current spikes from the power supplies. a parallel combination of capacitors, which have a low impedance over a wide frequency range should be used. a 4.7f tantalum capacitor in parallel with a low inductance 0.1f capacitor is usually sufficient bypassing. output damping ringing is a common problem in any circuit with very fast rise or fall times. such ringing will be aggravated by long inductive lines with capacitive loads. techniqu es to reduce ringing include: 1. reduce inductance by making printed circuit board traces as short as possible. 2. reduce inductance by using a ground plane or by closely coupling the output lines to their return paths. 3. use small damping resistor in series with the output of the isl55110 and isl55111. although this reduces ringing, it will also slightly increase the rise and fall times. 4. use good bypassing techniques to prevent supply voltage ringing. power dissipation calculation the power dissipation equation has three components: 1. quiescent power dissipation. 2. power dissipation due to internal parasitics. 3. power dissipation because of the load capacitor. power dissipation due to internal parasitics is usually the most difficult to accurately quantitize. this is primarily due to crowbar current which is a product of both the high and low drivers conducting effectively at the same time during driver transitions. design goals always target the minimum time for this condition to exist. given that how often this occurs is a product of frequency, crowbar effects can be characterized as internal capacitance. lab tests are conducted with driv er outputs disconnected from any load. with design verification packaging, bond wires are removed to aid in the characte rization process. based on laboratory tests and simulation correlation of those results, equation 1 defines the isl55110 and isl55111 power dissipation per channel: ? where 3.3ma is the quiescent current from the v dd . this forms a small portion of the total calculation. when figuring two channel power consumption, only include this current once. ? 10pf is the approximate parasitic capacitor (inverters, etc.), which the v dd drives. ? 135pf is the approximate parasitic at the d out and its buffers. this includes the effect of the crowbar current. ?c l is the load capacitor being driven. pv dd 3.3e-3 ? = 10pf v dd ? 2 f ? 135pf vh 2 ? ++ f ? + (eq. 1) cl vh 2 f ? ? (watts/channel)
isl55110, isl55111 14 fn6228.8 january 29, 2015 submit document feedback power dissipation discussion specifying continuous pulse rates, driver loads and driver level amplitudes are key in determining power supply requirements, as well as dissipation/cooling nece ssities. driver output patterns also impact these needs. the fast er the pin activity, the greater the need to supply current and remove heat. as detailed in the ? power dissipation calculation ? on page 13 , power dissipation of the device is calculated by taking the dc current of the v dd (logic) and v h current (driver rail) times the respective voltages and adding the product of both calculations. the average dc current measurements of i dd and ih should be done while running the device with the planned v dd and v h levels and driving the required pulse activity of both channels at the desired operating frequency and driver loads. therefore, the user must address power dissipation relative to the planned operating conditions . even with a device mounted per notes 4 or 5 under ?thermal information?, given the high speed pulse rate and amplitude capability of the isl55110 and isl55111, it is possible to exceed the +150c ?absolute maximum junction temperature?. th erefore, it is important to calculate the maximum junction temperature for the application to determine if operating conditions need to be modified for the device to remain in the safe operating area. the maximum power dissipation allowed in a package is determined according to equation 2 : where: ?t jmax = maximum junction temperature ?t amax = maximum ambient temperature ? ? ja = thermal resistance of the package ?p dmax = maximum power dissipation in the package the maximum power dissipation actually produced by an ic is the total quiescent supply current times the total power supply voltage, plus the power in the ic due to the loads. power also depends on number of channels changing state and frequency of operation. the extent of continuo us active pulse generation will greatly effect dissipation requirements. the user should evaluate variou s heatsink/cooling options in order to control the ambient temperature part of the equation. this is especially true if the user?s applications require continuous, high-speed operation. a review of the ? ja ratings of the tssop and qfn packages clearly show the qfn package to have better thermal characteristics. the reader is cautioned against assuming a calculated level of thermal performance in actual a pplications. a careful inspection of conditions in your application should be conducted. great care must be taken to ensure die temperature does not exceed +150c absolute maximum thermal limits. important note: the isl55110 and isl55111 qfn package metal plane is used for heat sinking of the device. it is electrically connected to ground (i.e., pin11). power supply sequencing apply v dd , then v h . power-up considerations digital inputs should never be un driven. do not apply slow analog ramps to the inputs. again, place decoupling caps as close to the package as possible for both v dd and especially v h . special loading with most applications, the user will usually have a special load requirement. please contact intersil for evaluation boards. p dmax t jmax - t amax ? ja -------------------------------------------- - = (eq. 2)
isl55110, isl55111 15 fn6228.8 january 29, 2015 submit document feedback revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change january 29, 2015 fn6228.8 page 1 , "description" section, 4th sentence, removed the wo rd "automotive" before the word piezoelectric". "applications", removed 3rd bullet item: "automotive piezo driver applications" may 30, 2014 fn6228.7 throughout document, changed ?hiz? to ?enable ? and ?pdn? pin references to ?pd?. page 2 , ?pin descriptions? table; changed ?function? entries for gnd and enable pins. added ep row. page 3 , ?ordering info? table; added ?tssop? or ?qfn? to the evaluation board entries to clarify. page 4 and page 5 ; changed ?driver output swing range? test conditions entry from ?vh voltage to ground? to ?oa or ob = ?1?, voltage referenced to gnd and changed ?driver supply quiescent current? ?test conditions? entry from ?no resistive load d out ? to ?outputs unloaded?. added ?figure 1? reference to the driver rise and fall time ?test conditions?. page 5 ; changed ?t en ? and ?t dis ? descriptions. figure 2 on page 6 : changed ?thresholds? to ?times? in title. figure 3 on page 6 : in ?tskewr? equation, changed ?chn 1? and ?chn 2? to ?chn a? and ?chn b? and added ?absolute value? indicator. figures 4 and 5 : changed ?resistance? to ?voltage? in titles. figures 6 and 7 : changed ?resistance? to ?voltage? in titles. figures 9 and 11 : added ?operating? to titles. figure 12 : fixed y-axis scale. figures 14 and 15 : added ?vs. vdd? to titles. figures 32 and 33 : changed x-axis label from ?v dd ? to ?vh?. figure 34 : added ?qfn? to title. ? power dissipation discussion ? on page 14 , changed ?it is electrically connected to the negative supply potential ground? to ?it is electrically connected to ground (i.e., pin11)? and, in the ?special loading? section, removed text ?or to request a device characte rization to your requirements in our lab?. august 8, 2013 fn6228.6 page 4 in electrical spec table changed units from ma to a ii_h input current logic high enable = vdd (qfn only)- july 9, 2012 fn6228.5 page 4 - removed ?recommended operating conditions tabl e?, which was located above dc electrical spec. table and placed in the abs max ratings table to meet intersil standards. page 5 - dc electrical spec: modified ih-pdn parameter (driver supply power-down current) max limit value from 1 to 2.5. added revision history table on page 15 . february 9, 2011 fn6228.4 for 8 ld tssop, added theta jc value of 46c/w. added foot note that for tssop package theta jc the case temp location is measured in the center of the top of the package. february 4, 2011 page 1: added following sentence to 3rd paragr aph: "both inputs of the device have independent inputs to allow external time phasing if required.? updated tape & reel note in ordering information on page 3 from ?add "-t" suffix for tape and reel.? to new standard ?add "-t*" suffix for tape and reel.? th e "*" covers all possible tape and reel options added msl note to ordering information page 5 : updated over temp note in min max column of sp ec tables from ?parameters with min and/or max limits are 100% tested at +25c, unless otherwis e specified. temperature limits established by characterization and are not production tested.? to ne w standard ?compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.? page 13 : changed equation 1 from: p vdd?3.3e-= 3+10pf?vdd2?f+135pf?vh2?f+ (eq. 1) cl?vh2?f (watts/channel) to p vdd 3.3e-= 3+10pf vdd2 f+135pf vh2 f+ cl vh2 (watts/channel) (eq. 1) page 14 : removed the following sentence from ?power supply sequencing?: ?the isl55110, isl55111 references both vdd and the vh driver supplies with respect to ground. therefore, apply vdd, then vh.? replaced with: ?apply vdd, then vh.? added subsection ?power up considerations? and moved text that was in the ?power supply sequencing? section to this section. (?digital inputs should?especially vh.?) page 18 - updated pod m8.173 as follows: updated to new pod standards as follows: moved dimens ions from table onto drawing. added land pattern. no dimension changes. march 14, 2008 fn6228.0 initial release
isl55110, isl55111 16 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6228.8 january 29, 2015 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support
isl55110, isl55111 17 fn6228.8 january 29, 2015 submit document feedback quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l16.4x4a 16 lead quad flat no-lead plastic package (compliant to jedec mo-220-vggd-10) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.18 0.25 0.30 5, 8 d 4.00 bsc - d1 3.75 bsc 9 d2 2.30 2.40 2.55 7, 8 e 4.00 bsc - e1 3.75 bsc 9 e2 2.30 2.40 2.55 7, 8 e 0.50 bsc - k0.25 - - - l 0.30 0.40 0.50 8 l1 - - 0.15 10 n162 nd 4 3 ne 4 3 p- -0.609 q- - 129 rev. 2 3/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in mill imeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measure d between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but m ust be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are for the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see inte rsil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & q are present whe n anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of t he package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
isl55110, isl55111 18 fn6228.8 january 29, 2015 submit document feedback package outline drawing m8.173 8 lead thin shrink small outline package (tssop) rev 2, 01/10 notes: end view detail "x" typical recommended land pattern top view b a c plane seating 0.10 c 0.10 c b a h 3.0 0.5 4.40 0.10 0.25 +0.05/-0.06 6.40 0.20 c b a 0.05 0-8 gauge plane see detail "x" 0.90 +0.15/-0.10 0.60 0.15 0.09-0.20 6 3 4 2 4 1.00 ref 0.65 1.20 max 0.25 0.05 min 0.15 max (5.65) (0.65 typ) (0.35 typ) (1.45) 1 c l pin 1 id mark 4 5 8 package body outline side view 2. dimension does not include mold flash, protrusions or gate burrs. mold flash, prot rusions or gate burrs shall 3. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.15 per sid e. 4. dimensions are measured at datum plane h. not exceed 0.15 per side. 5. dimensioning and toleranc ing per asme y14.5m-1994. 6. dimension on lead width does not include dambar protrusion. allowable protrusion shall be 0.08 mm total in excess of dimension at maximum material condition. minimum space between protrusion and adjacent lead is 0.07mm. 7. conforms to jedec mo-153, variation ac. issue e dimensions in ( ) for reference only. 1. dimensions are in millimeters.

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